1. Technical Field
Embodiments of the invention relate generally to delay lines and more particularly to delay cells with improved gain and reduced duty cycle distortion for a wide range of delays.
2. Prior Art
A delay line includes several delay cells connected in series that generate a required delay. Delay lines constitute several electronic devices, for example Delay Locked Loops (DLLs), which have a wide variety of electronic applications such as clock and data recovery, frequency synthesis, and generation of clock pulses for sampling in high speed Analog-to-Digital Converters (ADCs). A delay cell constitutes a building block of the delay line. The number of delay cells that the delay line makes use of depends on the required delay. It is therefore desirable that the delay cell supports a wide range of delays.
In order to sufficiently support the wide variety of applications, the delay line needs to have a wide range of operating frequencies. However, operating the delay line at high frequencies usually results in a loss of ‘gain’ and ‘duty cycle distortion’ in an output of a current or voltage controlled delay cell. The term gain refers to a variation in a delay of the delay cell with respect to a control voltage that controls a current through the delay cell. Duty cycle distortion may occur because of mismatch between rising and falling edge delays of the delay cell.
Some existing delay cells provide a reasonable gain over a limited delay range. In the application of this delay line in a DLL, the frequency range of operation of the DLL gets limited. Further, delay lines with large number of delay cells have considerable duty cycle distortion, thereby limiting the maximum number of delay cells that can be connected in series. To reduce the duty cycle distortion, a duty cycle control loop is used for which additional circuitry is required. This enhances chip area and power dissipation.
Existing delay lines that have the wide range of delay control make use of a current-starved inverter in the delay cell. A current starved inverter includes a NMOS and a PMOS current source. The delay of the delay cell is controlled by providing different voltage bias signals to control the current through the NMOS and PMOS current sources. However, the delay cell suffers from poor gain due to charge sharing between a load capacitance at an output of the delay cell and junction capacitances of the delay cell. One technique to reduce the charge sharing is to make the load capacitance value sufficiently greater than the drain junction capacitances. However, this results in an increase in minimum delay, switching power consumption, and die area.
Further in delay lines using current starved inverters, duty cycle distortion occurs due to mismatch between NMOS and PMOS current sources or non-symmetrical inverter trip point. As a result of this mismatch, pulse width of an output clock at the end of the delay line that uses N delay cells can expand or shrink by ‘N(Tdr−Tdf)’, where Tdr is the rising edge delay and Tdf is the falling edge delay. In case this value becomes greater than half the time period of an input clock to the delay line, no clock output will be obtained at end of the delay line.